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瑞萨电子 (Renesas Electronics Corporation)
Clock Multiplier And Jitter Attenuator

封装信息

CAD 模型:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG16
Lead Count (#):16
Pkg. Dimensions (mm):5.0 x 4.4 x 1.0
Pitch (mm):0.65

环境和出口类别

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)96
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Abs. Pull Range Min. (± PPM)115
C-C Jitter Typ P-P (ps)150
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)0.008 - 0.008, 0.015625 - 0.015625, 0.015734 - 0.015734, 0.151875 - 0.151875, 27 - 27
Input TypeLVCMOS
Inputs (#)2
Length (mm)5
MOQ192
Output Banks (#)1
Output Freq Range (MHz)10.368 - 10.368, 19.44 - 19.44, 27 - 27
Output TypeLVCMOS
Output Voltage (V)3.3
Outputs (#)1
Package Area (mm²)22
Pitch (mm)0.65
Pkg. Dimensions (mm)5.0 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryJitter Attenuators
Prog. ClockNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

描述

The 2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. A dual input mux is also provided. By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the input clock. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet system clock requirements. A loop bandwidth down to the Hz range is possible.