特性
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five and one bank of four outputs
- Separate output enable for each output bank
- Output Skew < 250ps
- Low jitter <200 ps cycle-to-cycle
- 2309A-1 for Standard Drive
- 2309A-1H for High Drive
- No external RC network required
- Operates at 3.3V VDD
- Available in SOIC and TSSOP packages
描述
The 2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2309A is a 16-pin version of the 2305A. The 2309A accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 2309A enters power down. In this mode, the device will draw less than 12uA for Commercial Temperature range and less than 25uA for Industrial temperature range, and the outputs are tri-stated. The 2309A is characterized for both Industrial and Commercial operation.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Product Category | Zero Delay Buffers |
