特性
- 8-pin SOIC package - Pb-free, RoHS compliant
- Absolute jitter ±100 ps
- Propagation Delay of ±600 ps
- Output multiplier of 2X
- Output clock frequency up to 80 MHz
- Can recover degraded input clock duty cycle
- Output clock duty cycle of 45/55
- Full CMOS clock swings with 25 mA drive capability at TTL levels
- Advanced, low power CMOS process
- Operating voltage of 3.3 V or 5 V
描述
The 2402 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase-Locked Loop (PLL) techniques. The chip is part of IDT's ClockBlocksTM family and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. The 2402 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.
支持社区
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14531频率偏移
Hi Dialog 我这边使用测试模式测出DA14531频率偏移40Hz，请问在软件中可以调整么？如何调整？
2020年12月15日 -
FCC认证测试遇到Duty cycle过低问题
... prodtest 连线方式，通过cable 连接频谱仪，从频谱仪观察 测试所用命令： prodtest -p 3 cont_pkt_tx 2402 37 4 ======================================================================================================================== 请教下：FCC 认证中该问题如何解决？谢谢！
2016年5月23日
