特性
- Low additive phase jitter RMS: 50fs
- Extremely low skew outputs (50ps)
- Low-cost clock buffer
- Packaged in an 8-SOIC and 8-DFN, Pb-free
- ICLK is PDT and may be driven before VDD is applied
- Direct-coupled signal path suitable for 1pps clocks
- Input/Output clock frequency up to 200MHz
- Non-inverting output clock
- Ideal for networking clocks
- Operating voltages: 1.8V to 3.3V
- Advanced, low-power CMOS process
- Extended temperature range: -40 °C to +105 °C
描述
The 524S is a low skew, single input to four output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.
产品参数
| 属性 | 值 |
|---|---|
| Function | Buffer |
| Outputs (#) | 4 |
| Output Type | LVCMOS |
| Output Freq Range (MHz) | 200 |
| Input Type | LVCMOS |
| Output Banks (#) | 1 |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Output Skew (ps) | 65 |
| Additive Phase Jitter Typ RMS (fs) | 35 |