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Clock Slicer User Configurable Zero Delay Buffer

封装信息

CAD 模型: View CAD Model
Pkg. Type: QSOP
Pkg. Code: PCG28
Lead Count (#): 28
Pkg. Dimensions (mm): 9.9 x 3.8 x 1.47
Pitch (mm): 0.64

环境和出口类别

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 28
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2500
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Advanced Features Feedback Input
Core Voltage (V) 3.3
Feedback Input Yes
Input Freq (MHz) 0.6 - 200
Input Type LVCMOS
Inputs (#) 1
Length (mm) 9.9
MOQ 2500
Output Banks (#) 2
Output Freq Range (MHz) 4 - 160
Output Skew (ps) 250
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 2
Package Area (mm²) 37.6
Period Jitter Typ P-P (ps) 90
Pitch (mm) 0.64
Pkg. Dimensions (mm) 9.9 x 3.8 x 1.47
Pkg. Type QSOP
Prog. Clock No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1.47
Width (mm) 3.8
已发布 No

描述

The 527-01 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-01 aligns rising edges on ICLK and FBIN at a ratio determined by the reference and feedback dividers. For configurable clocks that do not require zero delay, use the 525.