封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NDG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 3.0 x 3.0 x 1.0 |
| Pitch (mm): | 0.4 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 20 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Assembly Location | TAIWAN |
| Wafer Fab Location | TAIWAN |
| Additive Phase Jitter Typ P-P (ps) | 3 |
| Advanced Features | Programmable Clock, Reference Output, Spread Spectrum |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common |
| C-C Jitter Typ P-P (ps) | 50 |
| Core Voltage (V) | 1.8V |
| Family Name | VersaClock 3S |
| Feedback Input | No |
| Input Freq (MHz) | 1 - 160 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, HCSL |
| Inputs (#) | 1 |
| Length (mm) | 3 |
| Longevity | 2040 四月 |
| MOQ | 2500 |
| NXP Processor Function | Memory Clock, SerDes Clock, CPU/USB/Eth Clock |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 0.032768 - 125 |
| Output Type | LVCMOS, LP-HCSL |
| Output Voltage (V) | 1.8V |
| Outputs (#) | 5 |
| Package Area (mm²) | 9 |
| Phase Jitter Typ RMS (ps) | 3 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Product Category | VersaClock 3S, Low Jitter Clocks (<700 fs RMS), General Purpose Clocks, Programmable Clocks |
| Prog. Clock | Yes |
| Prog. Interface | I2C, OTP |
| Reel Size (in) | 13 |
| Reference Output | No |
| Selection Criteria | <700 fs RM |
| Spread Spectrum | Yes |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 3 |
| Xtal Freq (MHz) | 8 - 40 |
| Xtal Inputs (#) | 1 |
有关 5L35021 的资源
描述
The 5L35021 is a VersaClock® programmable clock generator designed for low-power, consumer, and high-performance PCI Express applications. The 5L35021 device is a three-PLL architecture design, and each PLL is individually programmable and allows for up to five unique frequency outputs.
The 5L35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, and then program the 5L35021 again through the I2C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pairs of differential outputs that support LVCMOS and LPHCSL. A low-power 32.768kHz clock is supported with less than 2μA current consumption for the system RTC reference clock.