特性
- Configurable OE pin function as OE, PD#, PPS, or DFC control function
- Configurable PLL bandwidth/minimizes jitter peaking
- PPS: Proactive Power Saving features save power during the end device power down mode
- PPB: Performance- Power Balancing feature allows minimum power consumption based on the required performance
- DFC: Dynamic Frequency Control feature allows up to 4 different frequencies to switch dynamically
- Features <65µA ultra-power-down
- Outputs: 1MHz to 125MHz
- Spread Spectrum clock support to lower system EMI
- I2C interface
- Supported by Renesas' Timing Commander™ software tool
描述
The 5L35021 is a VersaClock® programmable clock generator designed for low-power, consumer, and high-performance PCI Express applications. The 5L35021 device is a three-PLL architecture design, and each PLL is individually programmable and allows for up to five unique frequency outputs.
The 5L35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, and then program the 5L35021 again through the I2C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pairs of differential outputs that support LVCMOS and LPHCSL. A low-power 32.768kHz clock is supported with less than 2μA current consumption for the system RTC reference clock.
产品参数
| 属性 | 值 |
|---|---|
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Outputs (#) | 5 |
| Output Type | LVCMOS, LP-HCSL |
| Output Freq Range (MHz) | 0.032768 - 125 |
| Input Freq (MHz) | 1 - 160 |
| Inputs (#) | 1 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, HCSL |
| Output Banks (#) | 3 |
| Core Voltage (V) | 1.8 |
| Output Voltage (V) | 1.8 |
| Phase Jitter Typ RMS (ps) | 3 |
| Prog. Interface | I2C, OTP |
| Spread Spectrum | Yes |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 20 | 0.4 |
产品对比
| 5L35021 | 5L35023 | 5P35021 | 5P35023 | |
| Outputs (#) | 5 | 7 | 5 | 7 |
| Output Type | LP-HCSL, LVCMOS | LP-HCSL, LVCMOS | LP-HCSL, LVCMOS, LVDS, LVPECL | LP-HCSL, LVCMOS, LVDS, LVPECL |
| Core Voltage (V) | 1.8 | 1.8 | 3.3 | 3.3 |
| Output Voltage (V) | 1.8 | 1.8 | 1.8, 2.5, 3.3 | 1.8, 2.5, 3.3 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 1.0 | 4.0 x 4.0 x 0.9 | 3.0 x 3.0 x 1.0 | 4.0 x 4.0 x 0.9 |
应用
- Embedded computing devices
- Consumer application crystal oscillator replacements
- SmartDevice, handheld, and consumer applications
筛选
软件与工具
样例程序
模拟模型
A brief introduction to IDT's (acquired by Renesas) VersaClock 3S programmable clock generator IC features, benefits, and applications. These clock timing devices provide an optimal combination of performance, power, and flexibility.
IDT's VersaClock 3S devices meet the performance requirements of widely used standards including PCI Express® Gen 1/2/3. These new devices are ideal for computing systems, digital cameras, IP set-top boxes, home entertainment, audio systems, multi-function printers, IoT gateways, small-business storage, smart devices, medical equipment, and automotive infotainment.
Related Resources
The VersaClock 3S devices deliver innovative power-saving features while saving board space by eliminating the need for multiple discrete timing components. Delivering low power and low jitter scalability, the VersaClock 3S devices meet requirements for widely used standards including PCI Express® Gen 1/2/3, and are ideal for consumer, industrial, computing, and automotive applications.
The 5P35023 and 5P35021 chips deliver a unique set of features offering an optimal combination of performance, power, and flexibility.
Description
IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page.
Resources
IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.
Resources
IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.
Presented by Ron Wade, PCI Express timing expert.
新闻和博客
新闻
2017年8月14日
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