5L35021

The VersaClock 3S devices deliver innovative power-saving features while saving board space by eliminating the need for multiple discrete timing components. Delivering low power and low jitter scalability, the VersaClock 3S devices meet requirements for widely used standards including PCI Express^® Gen 1/2/3, and are ideal for consumer, industrial, computing, and automotive applications.

The 5P35023 and 5P35021 chips deliver a unique set of features offering an optimal combination of performance, power, and flexibility. 

Related Resources

• VersaClock Programmable Clocks

TRANSCRIPT

VersaClock 3S is a family of programmable clocks that deliver innovative features for an optimal blend of performance, power, and flexibility. The compact products can replace multiple crystals, or crystal oscillators, for a smaller board footprint while maintaining extremely low power consumption and are ideal for consumer, industrial, computing, and automotive applications.

VersaClock 3S offers less than three picoseconds of RMS phase jitter and supports PCI Express Generation 1, 2, and 3 requirements. A built-in, digitally controlled oscillator provides a low-frequency clock at less than two microamps per real-time clock operation with several years of operation using a coin-cell battery. Three PLLs optimized for different performance levels offer operation from 2mA to 15mA, and the device features several unique features to balance power and performance. Frequencies up to 160MHz on LVCMOS and up to 500MHz on differential outputs are supported and one-time programmable memory is available for programming.

The VersaClock 3S devices are offered in small 3mm x 3mm and 4mm x 4mm QFN packages. The larger device features three LVCMOS and two differential outputs along with a reference clock output. The smaller device offers a single LVCMOS and two differential clock outputs.

VersaClock 3S offers several unique features. A performance power balancing feature supported by the Renesas Timing Commander GUI easily optimizes power consumption based on target performance. A patented overshoot frequency control feature eliminates frequency overshoot or undershoot which is common with traditional PLL designs during frequency transitions. Dynamic frequency control offers smooth and glitch-free transitions between up to four pre-programmed frequencies for on-the-fly frequency changes.

And, VersaClock 3S is the world's first intelligent clock generator with a downstream device power-mode monitor. The proactive power-saving feature monitors the clock status using the Xout pin of the downstream device and will switch to a very low-power 32KHz clock during sleep mode and switch back to normal operation when the downstream device wakes up.

Other device features include a multi-function output that enables pins, along with a built-in watchdog timer. Evaluation and programmer boards along with our Timing Commander software are available to assist with development. The VersaClock 3S family offers an ideal combination of versatility, performance, and low power for a variety of applications. For more information, please visit www.renesas.com/versaclock. Thank you.

Description

IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page.

Transcript

Narrator: In a data driven world, timing is everything. That's why more and more system design engineers are using products from the world leader in silicon timing, IDT. IDT has earned its reputation for excellence by providing a wide range of leading technologies for wireless and wired communications infrastructure, high performance computing, and advanced power management.

And with a product portfolio 10 times greater than the competition, IDT is uniquely qualified to be your one-stop-shop for timing solutions. IDT's innovative Windows-based software platform, Timing Commander, makes it easy to configure, program, and monitor all your sophisticated timing devices.

Steven: What's great about IDT's Timing Commander is that it helps you avoid tedious manageable configurations so you can focus on other areas of your design.

Narrator: IDT's Timing Commander serves up intuitive configuration interfaces or personalities for all of IDT's programmable timing products. With a few simple clicks, you can generate a comprehensive, interactive block diagram and modified desired input values, output values, and other configuration settings. The software also writes your settings over USB to an IDT evaluation board for immediate application in the circuit. It really is as easy as one, two, three.

Steven: The Timing Commander software automatically makes calculations, monitors status, and prepares register settings so you don't have to reference a data sheet. Built-in documentation is readily available. Just hover over a setting, and real time validation ensures that the configuration complies with data sheet specifications. Whether you're a first time user or an experienced engineer, Timing Commander offers you the right amount of control.

Narrator: To help you program complex devices more intuitively, Timing Commander's advanced features include the ability to create phase noise estimates, generate the schematic symbol and termination circuit and determine the optimal balance between performance and power consumption.

Steven: Once your devices are configured and tuned for optimal system performance, you can save the configuration files for factory-level programming prior to shipment.

Narrator: Timing Commander is just one example of the innovative timing solutions IDT delivers.

Peter: From simple fanout buffers and multiplexers to fully featured products like universal frequency translators, network synchronization devices, and VersaClock families, IDT has a wide range of products optimized for specific applications. You can also count on IDT for the lowest jitter and lowest power features to help you build the world class products your customers demand.

Narrator: It's time to put IDT timing solutions to work for your business, and with the power of Timing Commander software, it's easier than ever. To learn more, visit IDT online or give us a call today.

Description

IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

So, hi there, this is Ron Wade again and we're going to be talking about timing solutions that IDT has for NXP's QorIQ and Layerscape CPU. And in the middle here, what I've drawn, in the middle of the box here, is what I refer to as our all-in-one solutions. These are single chips that may have all the clocks you need to build your system around the NXP CPUs. So, the three parts I have listed here are the 6P49V205, the 5P49V5907, and 5P49V5908. These provide a mix of the clocks that were needed over here for the CPU cores and SerDes clocks, and they're all on a single chip. If these suit your needs, these are ideal, these are the smallest core footprint parts to use. 
 
The other approach besides all-in-one is the building block approach, and I'm going to start over here on the left side with the CPU clocks and the memory controller. For this solution over here, we have the 5P49V5901, or it could be a 6901, depending on your requirements. And, this guy has the most flexibility as far as programming up any combination of DDR clock or CPU clock that you want, as well as the 24 MHz USB clock and a 125 MHz clock. 
 
If you're using the Layerscape CPU with the reduced oscillator mode where you have the 100 MHz non-spread clock coming in, you might want to consider the 9FGV0 series or the 9FGL0 series. These are very high-performance PCI Express clock generators, the V being a 1.8 volt part and the L being a 3.3 volt part that are available. The terminations are integrated, they're very low power and they also have some extra copies in case SerDes is a PCI Express SerDes. So, this is the ideal solution if you want to go building block over here. 
 
And then for the SerDes clocks, we've got the 125 MHz differential for Gigabit Ethernet, the 156 MHz for 10 gig, and the 100 MHz for PCIe. We have again a different set of flavors we can go with. We have the 5P49V6901, which is a better performing, lower phase jitter version of the 5901 over here. This guy's ideal if you have a mix of these SerDes frequencies in your design. If you're in a homogeneous environment, for instance, where everything's PCI Express or everything is 125 MHz, then you could use the 9FGV parts, or I'll use an output from over there, over on this side for the 100 MHz output, or you could use these guys programmed up to be 125 as well. Or if you've got a 125 coming from over there, you can use one of the 9DVD buffers which are the 1.8V buffers to fan that out. Likewise, we have similar parts with 3.3-volt power supplies, if that's what you prefer. The 9FGL0 series, it should give you the 100 to the 125, and the 9DVL0 series which can provide a fanout buffer for any of these three frequencies.
 
So, that's an overview of the timing solutions for NXP's QorIQ and Layerscape CPUs. This is Ron Wade at IDT again. Thanks for watching and see you next time.

IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

Hi there, this is Ron Wade with IDT and today we're going to talk about NXP, formerly known as Freescale, CPUs. Specifically the QorIQ and Layerscape CPUs and the timing requirements that they have. So, it's basically divided into a couple of parts here. There's some timing that the CPU itself requires and then there's timing that depends upon your system and the number of SerDes links you have in your design and in your CPU. So, if we talk about the CPU part itself, we have the CPU cores which get a clock, and we have the memory controller inside the CPUs which gets a clock as well. And the memory controller clock is called the DDR clock. The CPU clock is called the SYS_CCB clock in the Freescale nomenclature, excuse me, the NXP nomenclature and those frequencies - they're single-ended clocks and they range, like the DDR from 66.66 MHz up to 100 MHz, and the CPU clocks range from 66.66 up to 133.33 MHz, in some cases. Those are single-ended LVCMOS input clocks. Additionally, some of the CPUs have a USB interface which may require a 24 MHz single-ended clock. And there's also an Ethernet interface built in, a one-gigabit Ethernet interface, that is, takes a 125 MHz single-ended clock as well and that's at 2.5 volts.
 
So, in the Layerscape series of CPUs which are based on the ARM core, Freescale has put into them, what they call a reduced oscillator mode where all the clocks over here basically are reduced by a single differential 100 MHz non-spreading clock, and this saves you from having to figure out and generate all these clocks. However, it has to be non-spread because the USB clock is also derived from it, so, if you're planning to use spread spectrum, you really can't use this mode. And, currently, it's only available in the Layerscape devices, not the legacy QorIQ devices.
 
So, that's the basics for the CPU and the memory controller. Then the SerDes is really dependent upon the particular CPU you're using and how many SerDes lanes you need in your design. So, the SerDes clocks, on the other hand, basically range from 125 MHz differential clock for Gigabit Ethernet, if you're using 10 Gigabit Ethernet, a 156.25 MHz clock is required. And then if you're using PCI Express, you'd use a standard 100 MHz PCI Express clock. All these happen to be differential and the number of SerDes lanes and their capabilities depends on the CPU you're using. So, this gives you an outline of how to just do a quick tally of what kind of clocks you need and in another video, I'll talk about the solutions that IDT has for NXP's devices.