特性
- 4 differential outputs LVPECL, LVDS, HCSL - or 4 LVCMOS outputs
- <0.7ps RMS typical phase jitter on outputs
- Four fractional output dividers (FODs)
- Independent spread spectrum capability on each output pair
- Stores 4 different configurations in OTP non-volatile memory
- Up to 350MHz input/output frequencies
- Redundant clock inputs with manual switchover
- Programmable loop bandwidth, output to output skew, slew rate control
- Individual output enable/disable
- Meets PCIe® Gen 1/2/3, USB 3.0, 1/10 GbE clock requirements
- 1.8/2.5/3.3V core and output voltages
- 4mm x 4mm 24-pin VFQFPN package
- -40 °C to +85 °C operating temperature range
- Supported by Renesas' Timing Commander™ software tool
描述
The 5P49V5935 is a programmable clock generator intended for high-performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using an I²C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock® 5). The 5P49V5935, by default, uses an integrated 25MHz crystal as an input reference. It also has a redundant external clock input. A glitchless manual switchover function allows the selection of either input reference during normal operation.
Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe), or system production margin testing. The device may be configured to use one of two I²C addresses to allow multiple devices to be used in a system.
应用
- Ethernet switch/router
- PCI Express 1.0/2.0/3.0
- Broadcast video/audio timing
- Multi-function printer
- Processor and FPGA clocking
- Any-frequency clock conversion
- MSAN/DSLAM/PON
- Fiber Channel, SAN
- Telecom line cards
- 1GbE and 10GbE
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软件与工具
样例程序
模拟模型
Patrice Cater and Baljit Chandhoke introduce IDT's (acquired by Renesas) VersaClock 5 with an integrated crystal, emphasizing its compact design, ease of integration, and cost efficiency. They showcase its performance and versatility on an evaluation board, highlighting the device's ability to eliminate external frequency tuning components and its low power consumption. Available in two models, further details are accessible on Renesas's Programmable Clocks page.
Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer shows phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information visit the Programmable Clocks page.
This video will show you how to program VersaClock® 5 Low Power Programmable Clock Generator.
Description
IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page.
Resources
IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.
Resources
IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.
Presented by Ron Wade, PCI Express timing expert.
新闻和博客
新闻
2015年5月25日
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