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特性

  • < 100mW core power (at 3.3V)
  • < 0.5ps RMS phase jitter (typical)
  • Meets PCIe® Gen 1–4, USB 3.0, 1/10 GbE clock requirements
  • Supports both crystal (8MHz – 40MHz) and external clock input (1MHz – 350MHz)
  • 4 universal output pairs: LVPECL, LVDS, HCSL, or 8 LVCMOS outputs
  • 4 independent frequencies with 0.001MHz – 350MHz output range
  • Reference output
  • 1.8V/2.5V/3.3V core and output voltages
  • 2 programmable I²C addresses allowing multiple devices to be used in the same system
  • Up to 4 different configuration sets in OTP non-volatile memory
  • Supported by the Renesas IC Toolbox (RICBox) software tool
  • Quick sampling and customization process supported by online form submission
  • 4mm x 4mm 24-VFQFPN wettable flank package
  • AEC-Q100 qualified
  • -40°C to +105°C operating temperature range

描述

The 5P49V60 is a member of Renesas' VersaClock® 6E programmable clock generator family. The 5P49V60 is intended for automotive applications such as infotainment, dashboard, video processing, and in-vehicle networking, as well as applications based on PCI-Express or USB 3.0. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.

Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using the I²C interface.

产品参数

属性
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5
Outputs (#) 5
Output Type LVCMOS, LVPECL, HCSL, LVDS
Output Freq Range (MHz) -
Input Freq (MHz) -
Inputs (#) 2
Input Type Crystal, LVCMOS, LVPECL, LVDS, HCSL
Output Banks (#) 4
Core Voltage (V) 1.8, 2.5, 3.3
Output Voltage (V) 1.8, 2.5, 3.3
Phase Jitter Typ RMS (ps) 0.5
Prog. Interface I2C, OTP
Spread Spectrum Yes

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 4.0 x 4.0 x 0.9 24 0.5

应用方框图

Connected Android Cluster Block Diagram
Android 系统互联车载仪表
采用 Android 系统的汽车驾驶舱,具有无线连接和实时显示功能。
Communication Gateway and Integrated DVR/DMS System Solution Block Diagram
通信网关和集成 DVR/DMS 系统
融合 CoGW 与 DVR/DMS 视频处理功能的集成式汽车网关解决方案。
Full Digital Cluster Solution with AHL Block Diagram
高性价比数字集群,配备四通道 AHL 和环视功能
数字集群通过集中信息并通过 AHL 和高效的 PMIC 降低成本来提高安全性。
Automotive Cockpit Solution with Haptics Block Diagram
支持触觉反馈的汽车座舱系统
先进的座舱系统,配备新一代触觉反馈技术、BroadLED 驱动器和 PMIC。
Tire Pressure Monitoring System Block Diagram
胎压监测系统
低功耗蓝牙 LE TPMS 设计,集成了 PMIC,可降低成本、缩小尺寸和缩短开发时间。
Parking Assistance System with AHL Camera Block Diagram
带 AHL 摄像头的泊车辅助系统
具有高清模拟链路的汽车泊车摄像头系统降低了布线成本并保持零延迟。
Connected Gateway for Future E/E Architecture Block Diagram
未来 E/E 架构的互联网关
瑞萨电子通过 R-Car SoC、MCU、实时任务和连接支持实现先进的 E/E 汽车架构。
ADAS Front Camera Solution Block Diagram
ADAS 前置摄像头系统
可扩展的 ADAS 前置摄像头系统,具备符合 NCAP 要求的功能和高效深度学习性能。
High-End Cockpit & Infotainment Solution Block Diagram
高端驾驶舱和信息娱乐系统解决方案

当前筛选条件

The VersaClock® 6E programmable clock generator devices offer a combination of low power, flexibility and performance for a wide range of applications. These features make it ideal for simplifying system design by replacing multiple discrete timing components and reducing bill of materials (BOM). The VersaClock 6E supports operating voltages from 1.8 to 3.3 V, differential (LVPECL/HCSL/LVDS/LP-HCSL) and LVCMOS output types, and fractional dividers to accurately generate virtually any frequency. Products satisfy system requirements from oscillator replacement to PCIe® Gen 1/2/3 and to communications applications, while consuming very little power.

For more information about VersaClock 6E, visit the VersaClock Programmable Clocks page.