封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PAG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 12.5 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 48 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Core Voltage (V) | 1.8V, 2.5V |
| Input Type | HSTL, eHSTL, LVCMOS, LVEPECL |
| Output Skew (ps) | 125 |
| Output Voltage (V) | 1.8V, 2.5V |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 39 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Function | Buffer |
| Input Freq (MHz) | 250 |
| Inputs (#) | 1 |
| Length (mm) | 12.5 |
| MOQ | 78 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 250 |
| Output Type | LVCMOS |
| Outputs (#) | 10 |
| Package Area (mm²) | 76.3 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 12.5 x 6.1 x 1.0 |
| Pkg. Type | TSSOP |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
| 已发布 | No |
有关 5T907 的资源
描述
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T907 has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.