特性
- Four internal PLLs
- Internal non-volatile EEPROM
- Fast (400kHz) mode I2C serial interface
- Input frequency range: 1 MHz to 200 MHz
- Output frequency range: 4.9 kHz to 200 MHz
- Reference crystal input with programmable linear load capacitance - Crystal frequency range: 8 MHz to 50 MHz
- Four independently controlled VDDO (1.8V - 3.3V)
- Each PLL has a 7-bit reference divider and a 12-bit feedback-divider
- 8-bit output-divider blocks
- Fractional division capability on one PLL
- Two of the PLLs support spread spectrum generation capability
- I/O Standards: - Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS - Inputs - 3.3 V LVTTL/ LVCMOS
- Programmable slew rate control
- Programmable loop bandwidth
- Programmable output inversion to reduce bimodal jitter
- Redundant clock inputs with auto and manual switchover options
- Individual output enable/disable
- Power-down mode
- 3.3V core VDD
- Available in VFQFPN package
- -40 to +85 C Industrial Temp operation
描述
The 5V49EE904 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE904 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.
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Description
This video provides an overview of IDT's VersaClock® 3 and VersaClock LP product families. VersaClock programmable clock generators allow designers to save board space and cost by replacing crystals, oscillators (including programmable oscillators), and buffers with a single timing device. IDT's VersaClock product portfolio contains parts with up to four internal PLLs, each individually programmable, allowing for up to seven unique frequencies. Various subsets of the VersaClock family are targeted for different applications. For high-reliability systems, the VersaClock III family supports glitch-less automatic or manual switchover functions allowing the redundant clock to be selected during normal operation. For consumer systems, VersaClock III and LP (low power) provide flexibility with an internal EEPROM that makes it simple to reprogram frequencies for changing system requirements through the use of the I2C interface. Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about Renesas's VersaClock programmable clock generators, visit the Programmable Clocks page.
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