特性
- Configurable OE pin function as OE, PD#, PPS, or DFC control function
- Configurable PLL bandwidth/minimizes jitter peaking
- PPS: Proactive Power Saving features save power during the end device power down mode
- PPB: Performance Power Balancing feature allows minimum power consumption based on the required performance
- DFC: Dynamic Frequency Control feature allows up to 4 different frequencies to switch dynamically
- Spread spectrum clock support to lower system EMI
- I2C interface
- Also supports crystal input
- Supported by Timing Commander™ software tool
- Available in AEC-Q100 qualified, Grade 2 (-40 °C to +105 °C) version
描述
The 5P35021 is a VersaClock® programmable clock generator designed for low-power, consumer, and high-performance PCI Express applications. The 5P35021 device is a three-PLL architecture design, and each PLL is individually programmable allowing for up to five unique frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshoot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after powering up, and then program the 5P35021 again through the I2C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pairs of differential outputs that support LVCMOS, LVPECL, LVDS, and LPHCSL. A low-power 32.768kHz clock is supported with only less than 5μA current consumption for the system RTC reference clock.
产品对比
| 5P35021 | 5L35021 | 5L35023 | 5P35023 | |
| Outputs (#) | 5 | 5 | 7 | 7 |
| Output Type | LP-HCSL, LVCMOS, LVDS, LVPECL | LP-HCSL, LVCMOS | LP-HCSL, LVCMOS | LP-HCSL, LVCMOS, LVDS, LVPECL |
| Core Voltage (V) | 3.3 | 1.8 | 1.8 | 3.3 |
| Output Voltage (V) | 1.8, 2.5, 3.3 | 1.8 | 1.8 | 1.8, 2.5, 3.3 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 1.0 | 3.0 x 3.0 x 1.0 | 4.0 x 4.0 x 0.9 | 4.0 x 4.0 x 0.9 |
产品参数
| 属性 | 值 |
|---|---|
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Outputs (#) | 5 |
| Output Type | LVCMOS, LVPECL, LP-HCSL, LVDS |
| Output Freq Range (MHz) | 0.032768 - 500 |
| Input Freq (MHz) | 1 - 160 |
| Inputs (#) | 1 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, LP-HCSL |
| Output Banks (#) | 3 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 1.8, 2.5, 3.3 |
| Phase Jitter Typ RMS (ps) | 3 |
| Prog. Interface | I2C, OTP |
| Spread Spectrum | Yes |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 20 | 0.4 |
应用方框图
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