概览
描述
The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant input, making it ideal for level translation. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.
特性
- Low skew outputs (150 ps)
- Packaged in 8-pin SOIC or 8-pin DFN (2x2mm)
- RoHS 5 or RoHS 6 (lead-free) package
- Low power CMOS technology
- Operating voltages of 1.2 V to 1.8 V
- Output Enable pin tri-states outputs
- 3.3 V tolerant input clock
- Industrial or commercial temperature ranges
产品对比
应用
设计和开发
模型
ECAD 模块
点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。
模型
| 模型 - IBIS | ZIP 7 KB | |
1 项目
|
||
产品选项
当前筛选条件
支持
支持社区
-
RZ/G2UL EVK iperf测试以太网速率低
... 11:29:34:020][ ID] Interval Transfer Bitrate Retr [11:29:34:022][ 5] 0.00-10.00 sec 531 MBytes 445 Mbits/sec 621 sender [11:29:34:041][ 5] 0.00-10.00 sec 530 MBytes 445 Mbits/sec receiver [11:29:34:041] [11:29 ...
2024年7月12日