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瑞萨电子 (Renesas Electronics Corporation)

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数据手册、文档以及样品订购仍将通过 Renesas.com 官网提供,直至 2026 年底。如需新设计、采购、技术支持以及产品咨询,请访问 SiTime.com 官网或发送电子邮件至 [email protected]。预计于 2026 年底前全面过渡至 SiTime。

PLL Building Block

封装信息

CAD 模型:View CAD Model
Pkg. Type:SOIC
Pkg. Code:DCG16
Lead Count (#):16
Pkg. Dimensions (mm):9.9 x 3.9 x 1.5
Pitch (mm):1.27

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)48
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFeedback Input
Core Voltage (V)3.3V, 5V
Feedback InputYes
Input Freq (MHz)0.001 - 8
Input TypeLVCMOS
Inputs (#)1
Length (mm)9.9
MOQ144
Output Banks (#)2
Output Freq Range (MHz)0.25 - 120
Output TypeLVCMOS
Output Voltage (V)3.3V, 5V
Outputs (#)2
Package Area (mm²)38.6
Period Jitter Max P-P (ps)250
Period Jitter Typ P-P (ps)150
Pitch (mm)1.27
Pkg. Dimensions (mm)9.9 x 3.9 x 1.5
Pkg. TypeSOIC
Product CategoryGeneral Purpose Clocks
Prog. ClockNo
Reference OutputNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1.5
Width (mm)3.9

描述

The 673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (the 674-01), the user can customize the clock to lock to a wide variety of input frequencies. The 673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power down feature which turns off the entire device. For applications that require low jitter or jitter attenuation, see the MK2069. For a smaller package, see the 663.