特性
- Dual-port allows simultaneous access of the same memory location
- Dual chip enables allow for depth expansion without external logic
- Easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports; fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus-matching compatibility
- Includes JTAG functionality on BGA package versions only
- LVTTL-compatible, single 3.3V (±150mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in a 128-pin TQFP, 208-ball fpBGA, and 256-ball BGA
- Industrial temperature range (–40 °C to +85 °C) is available
70V639 - Block Diagram
描述
The 70V639 is a high-speed 128K x 18 asynchronous dual-port static RAM designed to be used as a stand-alone dual-port RAM or as a combination Master/Slave dual-port RAM for 36-bit or more word systems. Using the Master/Slave dual-port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature controlled by the chip enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.
产品参数
| 属性 | 值 |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 18 |
| Density (Kb) | 2304 |
| Pkg. Code | BC256, BF208, BFG208, PKG128 |
| Interface | Async |
| I/O Type | 3.3 V LVTTL |
| Access Time (ns) | 10, 12 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 128K x 18 |
| Function | Busy, Interrupt, JTAG, Master, Slave |
