瑞萨电子 (Renesas Electronics Corporation)
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71V3579

过时

3.3V 256K x 18 Synchronous Flow-Through SRAM with 3.3V I/O

概览

The 71V3579 3.3V CMOS SRAM is organized as 256K x 18 and contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.

71V3579 - Block Diagram
71V3579 - Block Diagram
  • Fast access time 7.5ns up to 117MHz clock frequency
  • LBO input selects interleaved or linear burst mode
  • Self-timed write cycle with global write control (GW), byte write
  • Enable (BWE), and byte writes (BWx)
  • 3.3V core power supply
  • Power down controlled by ZZ input
  • 3.3V I/O
  • Available in a 100-pin TQFP package

文档

设计和开发

ECAD 模块

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扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
71v3579_BG IBIS Model
ZIP 9 KB
模型 - IBIS
71V3579_PF IBIS Model
ZIP 9 KB
模型 - Verilog
71V3579 Verilog Model
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