概览
描述
The 71V3579 3.3V CMOS SRAM is organized as 256K x 18 and contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
特性
- Fast access time 7.5ns up to 117MHz clock frequency
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte write
- Enable (BWE), and byte writes (BWx)
- 3.3V core power supply
- Power down controlled by ZZ input
- 3.3V I/O
- Available in a 100-pin TQFP package
