特性
- Supports high-performance system speed
- Commercial and Industrial
- — 5ns Clock-to-Data Access (100MHz)
- — 6ns Clock-to-Data Access (83MHz)
- — 7ns Clock-to-Data Access (66MHz)
- Single-cycle deselect functionality (Compatible with
- Micron Part # MT58LC32K32D7LG-XX)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte
- write enable (BWE), and byte writes (BWx)
- Power down controlled by ZZ input
- Operates with a single 3.3V power supply (+10/-5%)
- Available in 100-pin TQFP package
描述
The 71V432 3.3V CMOS high-speed CacheRAM is organized as 32K x 32. The pipelined burst architecture provides cost effective 3-1-1-1 secondary cache performance for processors up to 100 MHz. The 71V432 CacheRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the CacheRAM.