概览
描述
The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
特性
- High system speed 4.5ns clock access time (117 MHz)
- Single-cycle deselect functionality (Compatible with
- Micron Part # MT58LC64K32D7LG-XX)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte
- write enable (BWE), and byte writes (BWx)
- Power down controlled by ZZ input
- Operates with a single 3.3V power supply (+10/-5%)
- Available in 100-pin TQFP package
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应用
设计和开发
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