概览
描述
The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
特性
- High system speed 4.5ns clock access time (117 MHz)
- Single-cycle deselect functionality (Compatible with
- Micron Part # MT58LC64K32D7LG-XX)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte
- write enable (BWE), and byte writes (BWx)
- Power down controlled by ZZ input
- Operates with a single 3.3V power supply (+10/-5%)
- Available in 100-pin TQFP package
产品对比
应用
设计和开发
模型
ECAD 模块
点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。
模型
| 模型 - IBIS | ZIP 9 KB | |
| 模型 - Verilog | ZIP 15 KB | |
2 项目
|
||
产品选项
当前筛选条件
