特性
- Ideal for the following applications:
- Network switching
- Two level prioritization of parallel data
- Bidirectional data transfer
- Bus
- matching between 18
- bit and 36
- bit data paths
- Width expansion to 36
- bit per package
- Depth expansion to 8,192 words per package
- 10ns read/write cycle time, 6.5ns access time
- IDT Standard or First Word Fall Through timing
- Single or double register buffered Empty and Full Flags
- Easily expandable in depth and width
- Asynchronous or coincident Read and Write clocks
- Async or sync programmable Almost Empty and Almost Full flags with default settings
- Half
- Full flag capability
- Available in 128-pin TQFP and 121 PBGA packages
- Industrial temperature range (–40C to +85C) is available
72805 - Block Diagram
描述
The 72805 is a 256 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72205 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
