特性
- Optimal combination capacity , speed and design flexibility in a small footprint
- 10 ns read/write cycle time
- 5V input tolerant
- IDT Standard or First Word Fall Through timing
- Single or double register-buffered Empty and Full Flags
- Easily expandable in depth and width
- Asynchronous or coincident Read and Write Clocks
- Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings
- Half-Full flag capability
- Output enable puts output data bus in high-impedance state
- Available in 128-pin TQFP
- Industrial temperature range (–40C to +85C) is available
72V805 - Block Diagram
描述
The 72V805 is a 256 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V205 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
