810N252I-02

The 810N252I-02 device uses Renesas' fourth generation FemtoClock^® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 810N252I-02 is a PLL-based synchronous multiplier optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation.

The 810N252I-02 contains two internal frequency multiplication stages that are cascaded in series. The first stage is a jitter attenuator, capable of jitter attenuation down to 10Hz using the external loop filter. The second stage is a FemtoClock NG frequency multiplier that provides the low jitter, high-frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. It is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.