特性
- Nine outputs, organized in three independent output banks with differential LVPECL and single-ended outputs
- One differential input clock can accept the following differential input levels: LVDS, LVPECL, LVHSTL
- One single-ended clock input
- Frequency generation optimized for wireless infrastructure
- Attenuates the phase jitter of the input clock signal by using low-cost pullable fundamental mode crystal (XTAL)
- Internal FemtoClock frequency multiplier stage eliminates the need for an expensive external high-frequency VCXO
- LVCMOS levels for all control I/O
- RMS phase jitter at 122.88MHz, using a 30.72MHz crystal (12kHz to 20MHz): 1.1ps RMS (typical)
- RMS phase jitter at 61.44MHz, using a 30.72MHz crystal (12kHz to 20MHz): 0.97ps RMS (typical)
- VCXO PLL bandwidth can be optimized for jitter attenuation and reference frequency tracking using external loop filter components
- PLL fast-lock control
- PLL lock detect output
- Absolute pull range is ± 50ppm
- Full 3.3V supply voltage
- -40 °C to 85 °C ambient operating temperature
- Available in a lead-free (RoHS 6) package
描述
The 813078I is a PLL-based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation are needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage attenuates the reference clock jitter by using an internal or external VCXO circuit. The internal VCXO requires the connection of an external inexpensive pullable crystal (XTAL) to the 813078I. This first PLL stage (VCXO PLL) uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The output of the first stage VCXO PLL is a stable and jitter-tolerant 30.72MHz reference input for the second PLL stage. The second PLL stage provides frequency translation by multiplying the output of the first stage up to 491.52MHz or 614.4MHz. The low phase noise characteristics of the VCXO-PLL clock signal are maintained by the internal FemtoClock® PLL, which requires no external components or complex programming. Two independently configurable frequency dividers translate the internal VCO signal to the desired output frequencies. All frequency translation ratios are set by device configuration pins. Supported input reference clock frequencies: 10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz, 61.44MHz, and 122.88MHz Supported output clock frequencies: 30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz, 153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz