特性
- Eight selectable 100MHz or 125MHz clocks for PCI Express™ and sRIO, HCSL interface levels
- One 156.25MHz SGMII clock, LVPECL interface levels
- Three LVCMOS/LVTTL outputs, 20Ω output impedance
- Selectable external crystal or differential (single-ended) input source
- Crystal oscillator interface designed for 25MHz, parallel resonant crystal
- Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels
- Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
- Output supply voltage modes:
VDD / VDDO
3.3V/3.3V
3.3V/2.5V - Full 3.3V output supply mode (HCSL)
- PCI Express™ (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
描述
The 8413S08I is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the PCI/PCI-X/PCIe bus clocks, the clocks for both the Gigabit Ethernet MAC and PHY and also the optional SGMII clock. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN56xx series of processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The industrial temperature range of the 8413S08I supports tele- communication, networking, and storage requirements.
产品参数
| 属性 | 值 |
|---|---|
| Outputs (#) | 15 |
| Output Type | HCSL, LVPECL, LVCMOS |
| Output Freq Range (MHz) | 25 - 25, 33.3 - 33.3, 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 |
| Input Freq (MHz) | 25 - 25 |
| Inputs (#) | 2 |
| Input Type | LVCMOS, Crystal |
| Output Banks (#) | 5 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3V, 2.5V |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 8.0 x 8.0 x 0.85 | 56 | 0.5 |