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Clock Generator For Cavium Processors

封装信息

CAD 模型: View CAD Model
Pkg. Type: VFQFPN
Pkg. Code: NLG56
Lead Count (#): 56
Pkg. Dimensions (mm): 8.0 x 8.0 x 0.85
Pitch (mm): 0.5

环境和出口类别

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 56
Carrier Type Tray
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 0
Qty. per Carrier (#) 260
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
C-C Jitter Max P-P (ps) 80
C-C Jitter Typ P-P (ps) 30
Core Voltage (V) 3.3
Feedback Input No
Input Freq (MHz) 25 - 25
Input Type LVCMOS, Crystal
Inputs (#) 2
Length (mm) 8
MOQ 260
Output Banks (#) 5
Output Freq Range (MHz) 25 - 25, 33.3 - 33.3, 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25
Output Signaling HCSL, LVPECL, LVCMOS
Output Skew (ps) 20
Output Type HCSL, LVPECL, LVCMOS
Output Voltage (V) 3.3V, 2.5V
Outputs (#) 15
Package Area (mm²) 64
Phase Jitter Max RMS (ps) 0.38
Phase Jitter Typ RMS (ps) 0.26
Pitch (mm) 0.5
Pkg. Dimensions (mm) 8.0 x 8.0 x 0.85
Pkg. Type VFQFPN
Prog. Clock No
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Tape & Reel No
Thickness (mm) 0.85
Width (mm) 8
Xtal Freq (KHz) 25 - 25
Xtal Inputs (#) 1
已发布 No

描述

The 8413S08I is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the PCI/PCI-X/PCIe bus clocks, the clocks for both the Gigabit Ethernet MAC and PHY and also the optional SGMII clock. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN56xx series of processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The industrial temperature range of the 8413S08I supports tele- communication, networking, and storage requirements.