特性
- One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels
- Nine LVCMOS/ LVTTL outputs, 23Ω typical output impedance
- Selectable external crystal or differential input source
- Crystal oscillator interface designed for 25MHz, parallel resonant crystal
- Differential input pair (PCLK, nPCLK) accepts LVPECL, LVDS, CML, SSTL input levels
- Internal resistor bias on nPCLK pin allows the user to drive PCLK input with external single-ended (LVCMOS/ LVTTL) input levels
- Power supply modes: CORE / OUTPUT 3.3V / 3.3V LVDS, LVPECL, LVCMOS 3.3V / 2.5V LVCMOS
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
描述
The 8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the 8430S10I-03 supports telecommunication, networking, and storage requirements.
产品参数
| 属性 | 值 |
|---|---|
| Outputs (#) | 10 |
| Output Type | LVCMOS, LVDS, LVPECL |
| Output Freq Range (MHz) | 25 - 25, 33.333 - 33.333, 50 - 50, 66.667 - 66.667, 80 - 80, 83.333 - 83.333, 100 - 100, 125 - 125, 133.333 - 133.333 |
| Input Freq (MHz) | 25 - 25 |
| Inputs (#) | 2 |
| Input Type | Crystal, CML, LVCMOS, LVDS, LVPECL, SSTL |
| Output Banks (#) | 6 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 2.5V, 3.3V |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| PTQFP | 7.0 x 7.0 x 1.0 | 48 | 0.5 |