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Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer

封装信息

CAD 模型: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG20
Lead Count (#): 20
Pkg. Dimensions (mm): 6.5 x 4.4 x 1.0
Pitch (mm): 0.65

环境和出口类别

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 20
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 3000
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Additive Phase Jitter Typ RMS (fs) 146
Additive Phase Jitter Typ RMS (ps) 0.146
Core Voltage (V) 3.3
Function Buffer, Multiplexer
Input Freq (MHz) 800
Input Type CML, HCSL, HSTL, LVDS, LVPECL, SSTL
Inputs (#) 2
Length (mm) 6.5
MOQ 3000
Output Banks (#) 1
Output Freq Range (MHz) 800
Output Skew (ps) 100
Output Type LVDS
Output Voltage (V) 3.3
Outputs (#) 4
Package Area (mm²) 28.6
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.5 x 4.4 x 1.0
Pkg. Type TSSOP
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4
已发布 No

描述

The ICS8543-09 is a low-skew, high-performance 1-to-4 differential-to-LVDS clock fanout buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543-09 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The device has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8543-09 ideal for those applications demanding well-defined performance and repeatability.