概览
描述
The 854S036 is a low skew, high performance Dual Differential-to-LVDS Fanout Buffer. One of the two fanout buffers has 3 LVDS outputs, the other has 6 LVDS outputs. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The 854S036 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S036 ideal for those clock distribution applications demanding well defined performance and repeatability.
特性
- Two independent differential LVDS output buffers, buffer A with three outputs, buffer B with 6 outputs
- Two differential clock input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Output frequency: 2GHz
- Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
- Output skew: 100ps (maximum)
- Bank skew: 20ps (maximum)
- Propagation delay: 550ps (maximum)
- Additive phase jitter, RMS: 0.06ps (typical)
- Full 3.3V power supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
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