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瑞萨电子 (Renesas Electronics Corporation)
LVCMOS Clock Generator

封装信息

CAD 模型:View CAD Model
Pkg. Type:QSOP
Pkg. Code:PCG20
Lead Count (#):20
Pkg. Dimensions (mm):8.7 x 3.8 x 1.47
Pitch (mm):0.64

环境和出口类别

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)20
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)3000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFeedback Input
C-C Jitter Max P-P (ps)320
Core Voltage (V)3.3
Feedback InputYes
Input Freq (MHz)2.5 - 80
Input TypeLVCMOS
Inputs (#)1
Length (mm)8.7
MOQ3000
Output Banks (#)2
Output Freq Range (MHz)2.5 - 80
Output Skew (ps)300
Output TypeLVCMOS
Output Voltage (V)3.3
Outputs (#)6
Package Area (mm²)33.1
Pitch (mm)0.64
Pkg. Dimensions (mm)8.7 x 3.8 x 1.47
Pkg. TypeQSOP
Product CategoryZero Delay Buffers
Prog. ClockNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1.47
Width (mm)3.8
已发布No

描述

The 870931I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the reference clock. The device offers six outputs. The PLL loop filter is completely internal and does not require external components. Several combinations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The 870931I-01 device is a member of the family of high performance clock solutions from IDT.