特性
- Two differential LVDS output pairs
- One differential clock input
- CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
- Input frequency range: 98MHz to 128MHz
- Output frequency range: 98MHz to 640MHz
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 50ps (maximum)
- Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
描述
The 874002-02 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express®™ systems, such as those found in desktop PCs, the PCI Express®™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874002-02 has 2 PLL bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 3MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The 874002-02 can be set for differential modes using the F_SELx pins as shown in Table 3C. The 874002-02 uses IDT's 3RD Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.
