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瑞萨电子 (Renesas Electronics Corporation)
2.5V Differential Clock Divider/Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:TQFP
Pkg. Code:EDG64
Lead Count (#):64
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)64
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)160
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (fs)50
Additive Phase Jitter Typ RMS (ps)0.05
Adjustable PhaseNo
Advanced FeaturesIndividual output bank enable
Channels (#)1
Core Voltage (V)2.5
Divider Value1, 4
FunctionBuffer, Divider
Input Freq (MHz)650
Input TypeCML, LVDS, LVPECL, SSTL
Inputs (#)1
Length (mm)10
MOQ160
Output Banks (#)6
Output Freq Range (MHz)650, 162.5
Output Skew (ps)70
Output TypeLVPECL, LVDS
Output Voltage (V)2.5
Outputs (#)20
Package Area (mm²)100
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeTQFP
Product CategoryClock Buffers & Drivers, Clock Dividers, RF Buffers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5
Tape & ReelNo
Thickness (mm)1
Width (mm)10

描述

The 874328I-01 is a high-performance differential ÷1 and ÷4 clock divider and fanout buffer. The device is designed for the frequency-division and signal fanout of high-frequency, low phase-noise clock signals. The differential input signal is frequency divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks are provided with a total of twenty differential outputs. The 874328I-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 874328I-01 ideal for those clock distribution applications demanding well-defined performance and repeatability.