封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | DQG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 9.7 x 6.1 x 1.0 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 28 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 1000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Feedback Input, Reference Output |
| App Jitter Compliance | PCI/PCI-X |
| C-C Jitter Max P-P (ps) | 120 |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 8.33 - 41.67 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 9.7 |
| MOQ | 1000 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 8.33 - 166.67 |
| Output Skew (ps) | 65 |
| Output Type | LVCMOS, LVTTL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 6 |
| Package Area (mm²) | 47 |
| Period Jitter Max P-P (ps) | 20 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 9.7 x 6.1 x 1.0 |
| Pkg. Type | TSSOP |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
| 已发布 | No |
有关 87604I 的资源
描述
The 87604I is a 1:4 PCI/PCI-X Clock Generator. The 87604I has a selectable REF_IN or crystal input. The REF_IN input accepts LVCMOS or LVTTL input levels. The 87604I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". The PLL's VCO has an operating range of 250MHz - 500MHz, allowing this device to be used in a variety of general purpose clocking applications. For PCI/PCI-X applications in particular, the VCO frequency should be set to 400MHz. This can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback divide value. The divider on the output bank can then be configured to generate 33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3). The 87604I is characterized to operate with its core supply at 3.3V and the bank supply at 3.3V or 2.5V. The 87604I is packaged in a small 6.1mm x 9.7mm TSSOP body, making it ideal for use in space-constrained applications.