特性
- Fully integrated PLL
- Nine single ended 3.3V LVCMOS/LVTTL outputs
- Selectable single ended CLK0 or differential CLK1, nCLK1 inputs
- The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels
- CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Output frequency range: 25MHz to 180MHz
- VCO range: 200MHz to 480MHz
- External feedback for "zero delay" clock regeneration
- Cycle-to-cycle jitter: ±100ps (typical)
- Output skew: 375ps (maximum)
- PLL reference zero delay: 350ps window (maximum)
- 3.3V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS-compliant package
87951I - Block Diagram
描述
The 87951I is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Cock Generator. The CS87951I has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the 87951I is targeted for high performance clock applications. Along with a fully integrated PLL, the 87951I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
