特性
- Four independent timing channels
- Jitter output below 150fs RMS (typical)
- Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
- DPLLs/Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
- DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
- IEEE 1588 Support:
- Precise (1ps) resolution for phase measurement and control
- All outputs/inputs can be configured to decode/encode PWM clock signals
- PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive/non-revertive and other programmable settings
- Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I²C EPROM via separate I²C Master Port
描述
The 8A34013 line card synchronizer for IEEE 1588 regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media that introduce clock propagation delays. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for IEEE 1588 clock synthesis, SyncE clock generation, jitter attenuation, and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 4 |
| Outputs (#) | 8 |
| Output Type | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Input Freq (MHz) | 0.001 - 1000 |
| Inputs (#) | 4 |
| Input Type | HCSL, LVDS, LVHSTL, LVPECL, SSTL |
| Output Banks (#) | 4 |
| Core Voltage (V) | 2.5V, 3.3V |
| Output Voltage (V) | 1.2V, 1.5V, 1.8V, 2.5V, 3.3V |
| Product Category | IEEE 1588, ClockMatrix, Ultra-Low Jitter Clocks (<300 fs RMS), Jitter Attenuators, Network Synchronization, Programmable Clocks |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 7.0 x 7.0 x 0.8 | 48 | 0.5 |
Renesas Boards & Kits
Evaluation Kit for 8A34003 ClockMatrix
This is the evaluation kit for the 8A34003, 8A34004, 8A34013, and 8A34043. The 8A34003 is functionally a superset of these products, making it suitable to evaluate any of the four. Please return to the device product page for more information on each specific device. The 8A34003 provides four... 阅读详情
