封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 1.0 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 20 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | AUSTRIA |
| Additive Phase Jitter Typ RMS (fs) | 39 |
| Additive Phase Jitter Typ RMS (ps) | 0.039 |
| Adjustable Phase | No |
| Channels (#) | 1 |
| Core Voltage (V) | 1.8 |
| Family Name | 8P34S |
| Function | Buffer |
| Input Freq (MHz) | 1200 |
| Input Type | LVPECL, LVDS, CML |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| MOQ | 490 |
| Noise Floor (dBc/Hz) | -162 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1200 |
| Output Skew (ps) | 20 |
| Output Type | LVDS |
| Output Voltage (V) | 1.8V, 2.5V |
| Outputs (#) | 6 |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Price (USD) | $7.38243 |
| Product Category | Clock Buffers & Drivers, RF Buffers |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4 |
有关 8P34S1106 的资源
描述
The 8P34S1106 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase noise clock and data signals. The 8P34S1106 is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1106 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and six low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the differential device input. The device is optimized for low power consumption and low additive phase jitter.