特性
- Eight low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2GHz (maximum)
- LVCMOS/LVTTL interface levels for the control input (input select)
- Output skew: 8ps (typical)
- Propagation delay: 255ps (typical)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz to 20MHz: 65fs (typical)
- Maximum device current consumption (IDD): 170mA
- 2.5V supply voltage
- Lead-free (RoHS 6), 28-lead VFQFN packaging
- -40 °C to 85 °C ambient operating temperature
描述
The 8SLVD1208I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVD1208I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1208I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
For a 3.3V version of this device, please refer to the 8SLVD1208-33I.
