封装信息
| Lead Count (#) | 16 |
| Pkg. Code | NLG16 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 1.0 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Lead Count (#) | 16 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 624 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Country of Assembly | Malaysia |
| Country of Wafer Fabrication | Austria |
| Price (USD) | 1ku | 3.29788 |
| Additive Phase Jitter Typ RMS (fs) | 36 |
| Additive Phase Jitter Typ RMS (ps) | 0.036 |
| Adjustable Phase | No |
| Channels (#) | 1 |
| Core Voltage (V) | 2.5, 3.3 |
| Family Name | 8SLVP |
| Function | Buffer |
| Input Freq (MHz) | 0 - 2000 |
| Input Type | CML, LVDS, LVPECL |
| Inputs (#) | 1 |
| Length (mm) | 3 |
| Longevity | 2040 4月 |
| MOQ | 624 |
| Noise Floor (dBc/Hz) | -162 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 0 - 2000 |
| Output Skew (ps) | 15 |
| Output Type | LVPECL |
| Output Voltage (V) | 2.5, 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 9.0 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 3 |
描述
The 8SLVP1102 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVP1102 is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1102 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and two low-skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device input. The device is optimized for low power consumption and low additive phase noise.