特性
- Eight low-skew, low additive jitter LVPECL output pairs
- Two selectable, differential clock input pairs
- Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz
- LVCMOS interface levels for the control input (input select)
- Output skew: 28ps (typical)
- Propagation delay: 410ps (maximum)
- Low additive phase jitter, RMS: 54.1fs (maximum) (fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz)
- Full 3.3V and 2.5V supply voltage
- Maximum device current consumption (IEE): 141mA
- Available in a lead-free (RoHS 6), 28-lead VFQFN package
- -40 °C to 85 °C ambient operating temperature
8SLVP1208I - Block Diagram
描述
The 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low-skew outputs are available. The integrated bias voltage generators enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, Clock Multiplexers, RF Buffers |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.8 | 28 | 0.5 |
