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瑞萨电子 (Renesas Electronics Corporation)
2.5V LVDS 1:16 Clock Fanout Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG52
Lead Count (#):52
Pkg. Dimensions (mm):8.0 x 8.0 x 0.9
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)52
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)3000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Core Voltage (V)2.5
FunctionBuffer, Multiplexer
Input Freq (MHz)1000 - 1000
Input TypeLVTTL, LVPECL, HSTL, HCSL
Inputs (#)2
Length (mm)8
MOQ3000
Output Banks (#)2
Output Freq Range (MHz)1000 - 1000
Output SignalingLVDS
Output Skew (ps)50
Output TypeLVDS
Output Voltage (V)2.5
Outputs (#)16
Package Area (mm²)64
Pitch (mm)0.5
Pkg. Dimensions (mm)8.0 x 8.0 x 0.9
Pkg. TypeVFQFPN
Product CategoryClock Buffers & Drivers, Clock Multiplexers
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)0.9
Width (mm)8
已发布No

描述

The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS outputs. The fanout from a differential input to the sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 8T349316 can act as a translator from a differential HSTL, LVPECL, CML, or LVDS input to LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous changeover from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 8T349316 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. The extended temperature range supports wireless infrastructure, telecommunication, and networking end equipment requirements.