瑞萨电子 (Renesas Electronics Corporation)
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8T49N287

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FemtoClock NG Universal Frequency Translator (2-in/2-PLL/8-out)

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特性

  • Supports GR.1244 Stratum 3 stability in holdover mode
  • Compliant with the requirements outlined in Telcordia GR-253-CORE (SONET) & ITU-T G.813/G.8262 (SDH/SONET & SyncE) when paired with a Synchronous Equipment Timing Source (SETS ) device
  • Generates up to 8 LVPECL / LVDS/HCSL or 16 LVCMOS output clocks ranging from 8kHz up to 1.0 GHz (diff), 8 kHz to 250 MHz (LVCMOS), that meet jitter limits for 10G up to 100G Ethernet and STM-256/OC-768 applications
    • 0.3ps RMS (including spurs), 12 kHz to 20 MHz
  • Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input clocks ranging from 8 kHz up to 875 MHz
    • Auto and manual input clock selection with hitless switching
    • Clock input monitoring, including support for gapped clocks
  • Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients
  • Operates from a 10 MHz to 40 MHz fundamental-mode crystal
  • Register programmable through I2C / SPI or via external I2C EEPROM
  • 8T49N287-993 “Boot from EEPROM”
  • 8T49N287-994 “powers up disabled”
  • Supported by Timing Commander Software
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8T49N287 Functional Block Diagram
8T49N287 Pinout Diagram
8T49N287 Functional Block Diagram
8T49N287 Pinout Diagram

描述

The 8T49N287 has two fractional feedback PLL’s that can be used as a frequency translators with jitter attenuation or a frequency synthesizers. It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8 kHz to 1 GHz. Output frequencies can be completely independent of the input frequencies, and up to four of these frequencies can be completely independent of each other. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.

The 8T49N287 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or on test and measurement applications. The 8T49N287 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications in order to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card.

Renesas’ third generation Universal Frequency Translator family also includes the 8T49N285 (2-in / 1-PLL / 8-out), 8T49N286 (4-in / 2-PLL / 8-out), and the 8T49N242 (2-in / 1-PLL / 4-out). These devices are complemented by the 82P33714 and 82P33731 synchronous equipment timing source (SETS) for Synchronous Ethernet (SyncE) and 10G-40G SyncE, respectively.

To see other devices in this product family, visit the Universal Frequency Translators page.

产品参数

属性 值
Inputs (#) 2
Input Type LVCMOS, LVTTL, HCSL, LVHSTL, LVDS, LVPECL
Product Category FemtoClock NG
Diff. Outputs 8
Output Type LVCMOS, LVDS, LVPECL, HCSL
Output Voltage (V) 2.5, 3.3
Input Freq (MHz) 0.008 - 875
Phase Jitter Typ RMS (ps) 0.28
Output Freq Range (MHz) 0.008 - 1000
Fractional Output Dividers (#) 2
Core Voltage (V) 2.5, 3.3
Output Banks (#) 4
Loop Bandwidth Range (Hz) 0.5 - 360
Xtal Freq (KHz) 10000 - 40000
Advanced Features Programmable Hitless Reference Switching, Fractional-N PLL, External Feedback

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 8.0 x 8.0 x 0.85 56 0.5
此为出厂可配置设备。试用自定义部件配置工具。

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Description

Overview of IDT's third generation Universal Frequency Translator (UFT) family of timing devices for high-performance optical networks, wireless base stations, and 100 Gigabit Ethernet (GbE) interface applications. The new UFT devices are the industry's only single-chip programmable solutions capable of generating eight different output frequencies with less than 300 femtoseconds RMS phase jitter over the standard 12 kHz to 20 MHz integration range.
 
The IDT 8T49N28x UFT family of timing devices offers eight independently programmable clocking outputs with the flexibility to apply virtually any input frequency and select virtually any output frequency. The devices' high level of integration and low jitter eliminates the need for separate frequency translation, redundancy management, and jitter attenuation devices -- empowering system designers to save cost and board area by consolidating those functions into a single device. In addition, the device offers significant flexibility in configuration and ease of programmability with IDT's Timing Commander software, making it useful in a variety of sockets and modes of operation with minimal design effort.
 
Presented by Ian Dobson, Director of System Architecture at IDT. Visit the Universal Frequency Translators page for information.
 

新闻和博客

博客
2021年4月27日
Benefits of a Point-of-Use Clock for Jitter Optimization
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