封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG40 |
| Lead Count (#): | 40 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 40 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 105°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | SINGAPORE |
| Additive Phase Jitter Typ RMS (fs) | 50 |
| Core Voltage (V) | 3.3V, 2.5V |
| Function | Buffer |
| Input Freq (MHz) | 3000 |
| Input Type | LVPECL, LVDS |
| Inputs (#) | 1 |
| Length (mm) | 6 |
| MOQ | 490 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 3000 |
| Output Skew (ps) | 35 |
| Output Type | LVPECL, LVDS |
| Output Voltage (V) | 2.5V, 3.3V, 1.8V |
| Outputs (#) | 8 |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Price (USD) | $8.71952 |
| Prog. Interface | I2C |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 6 |
| 已发布 | No |
有关 8T79S308 的资源
描述
The 8T79S308 is a fully integrated signal fanout buffer for high-performance, low additive phase noise applications. The main function of the device is the distribution and fanout of high-frequency clocks or low-frequency synchronization signals. The 8T79S308 is optimized to deliver very low phase noise clocks and precise, low-skew outputs, low device-to-device skew characteristics and fast output rise/fall times help the system design to achieve deterministic clock phase relationship across devices.
The device distributes the input signals (IN_0, IN_1) to two fanout banks. A input select logic allows the device to operate as 1:8 buffer, dual 1:4 buffers, and to cross the input signals. The propagation delay in both outputs banks is designed for equal delay to support fixed phase relationships between both banks. All outputs are very flexible in LVPECL/LVDS output style configuration, output signal termination, and allow both DC and AC coupling. Outputs can be individually disabled through a serial interface.
The device is packaged in a lead-free (RoHS 6) 40-VFQFPN package. The extended temperature range supports wireless infrastructure, telecommunication, and networking end equipment requirements. The 8T79S308 is a member of the high-performance clock family from IDT.