封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 24 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Additive Phase Jitter Typ RMS (fs) | 65 |
| Additive Phase Jitter Typ RMS (ps) | 0.065 |
| Adjustable Phase | No |
| Advanced Features | 1PPS Clock multiplexer |
| Channels (#) | 1 |
| Core Voltage (V) | 2.5V, 3.3V |
| Function | Buffer |
| Input Freq (MHz) | 1000 |
| Input Type | LVDS, LVPECL, Sine Wave |
| Inputs (#) | 2 |
| Length (mm) | 4 |
| MOQ | 2500 |
| Noise Floor (dBc/Hz) | -152 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1000, 500, 250, 125 |
| Output Skew (ps) | 65 |
| Output Type | LVDS, LVCMOS |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 6 |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Product Category | Clock Buffers & Drivers, RF Buffers |
| Prog. Interface | Pin select |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 4 |
有关 8V34S204I 的资源
描述
The 8V34S204 is a differential 1:4 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock/1PPS, 2kHz and 8kHz signal distribution. Controlled by the input modes election pin, the differential input stages accept both rectangular or sinusoidal signals. The 8V34S204 also provides level-translated LVCMOS/LVTTL outputs which are copies of the individual differential inputs CLKA and CLKB. The propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. The multiplexer select pin (SEL) allows for the selection of one out of two input signals, which is copied to the four differential outputs.