特性
- Clock signal selection, frequency division, and distribution
- Two outputs individually select:
- The input signal ÷2, ÷4, ÷5, and ÷8
- The input signal without frequency division (input signal is passed through)
- Two inputs to support single-ended and differential operation
- Differential input supports LVDS and LVPECL signals
- Single-ended input supports LVCMOS signals
- Two differential LVDS outputs
- Maximum input frequency (differential input clock): 2000MHz
- Maximum output frequency: 2000MHz
- Output skew: 22ps (maximum)
- Additive phase noise RMS, 12kHz to 20MHz integration range: 14fs (typical)
- LVDS output rise/fall time: 260ps (maximum)
- 3.3V core and output supply voltages
- -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) 4mm x 4mm2 20-lead VFQFN packaging
描述
The 8V74S4622 is a versatile clock fanout buffer/frequency divider. The device supports the selection, division, and distribution of high-frequency clock signals with very low additive phase noise. The 8V74S4622 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection and internal isolation.
Two selectable inputs are supported for differential and single-ended clocks. Each of the two outputs can select a copy or a frequency-divided input signal. The available frequency divisions are divided by 2, 4, 5, and 8. Both outputs support LVDS interfaces. For each of the two outputs, a synchronous output-enabled control is implemented for stopping the output clock synchronously to the input clock signal. All device configurations are through a logic pin interface. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.
