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瑞萨电子 (Renesas Electronics Corporation)

瑞萨电子的时序产品组合已被 SiTime 收购。

数据手册、文档以及样品订购仍将通过 Renesas.com 官网提供,直至 2026 年底。如需新设计、采购、技术支持以及产品咨询,请访问 SiTime.com 官网或发送电子邮件至 [email protected]。预计于 2026 年底前全面过渡至 SiTime。

特性

  • Two LVPECL output pairs Each output supports independent frequency selection at 25MHz, 125MHz and 156.25MHz
  • One differential input supports the following input types: LVPECL, LVDS
  • Accepts input frequencies 8kHz, 25MHz,125MHz and 155.52MHz
  • First stage PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection
  • FemtoClock frequency multiplier provides low jitter, high frequency output
  • Absolute pull range: 50ppm
  • FemtoClock VCO frequency: 625MHz
  • RMS phase jitter @ 25MHz, using a 25MHz crystal (12kHz '- 5MHz): 0.238ps (typical), 0.30ps (maximum)
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz '- 20MHz): 0.223ps (typical), 0.30ps (maximum)
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz '- 20MHz): 0.223ps (typical), 0.30ps (maximum)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

描述

The 8V89308I is a PLL based synchronous multiplier specifically designed for applications utilizing Broadcom PHYs and Switches. This high performance device is optimized for Ethernet / SONET PDH frequency translation and clock jitter attenuation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a low bandwidth PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in Ethernet, SONET, PDH applications. 8V89308I requires the use of an external, inexpensive fundamental mode crystal and uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range.

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