特性
- 3 Differential CPU Clock Pairs @ 3.3V
- 7 PCI (3.3V) @ 33.3MHz
- 3 PCI_F (3.3V) @ 33.3MHz
- 1 USB (3.3V) @ 48MHz
- 1 DOT (3.3V) @ 48MHz
- 1 REF (3.3V) @ 14.318MHz
- 5 3V66 (3.3V) @ 66.6MHz
- 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
- Supports spread spectrum modulation, down spread 0 to -0.5%.
- Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#.
- Uses external 14.318MHz crystal
- Stop clocks and functional control available through I2C interface.
- CPU Output Jitter 150ps
- 3V66 Output Jitter 250ps
- CPU Output Skew 100ps, programmable over 800 ps with groups CPU0,1 and CPU2.
950201 - Block Diagram
描述
Programmable Timing Control Hub™ for P4™
