封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 9.7 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 28 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 50 |
| Chipset Name | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle |
| Input Freq (MHz) | 100 - 200 |
| Output Voltage (V) | 0.8 |
| Package Area (mm²) | 42.7 |
| Pkg. Dimensions (mm) | 9.7 x 4.4 x 1.0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Accepts Spread Spec Input | Yes |
| Advanced Features | HW PLL mode control |
| App Jitter Compliance | PCIe Gen1 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 50 |
| C-C Jitter Typ P-P (ps) | 35 |
| Chipset Manufacturer | Intel |
| Clock Spec. | DB400 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 4 |
| Diff. Termination Resistors | 16 |
| Feedback Input | No |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 9.7 |
| MOQ | 2000 |
| Multiplication Value | 1 |
| Multiply/Divide Value | 2 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 10 - 400 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Outputs (#) | 4 |
| PLL | Yes |
| Pitch (mm) | 0.65 |
| Pkg. Type | TSSOP |
| Platform Name | Bensley, Caneland, Glidewell, Lindenhurst, Truland |
| Power Consumption Typ (mW) | 300 |
| Prog. Clock | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
| 已发布 | No |
有关 9DB401 的资源
描述
The 9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the 952601, 954101 or 954201. It provides outputs meeting tight cycle-to-cycle jitter (50 ps) and output-to-output skew (50ps) requirements.