封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Jitter | 13fs |
| Additive Phase Jitter Typ RMS (fs) | 300 |
| Additive Phase Jitter Typ RMS (ps) | 0.3 |
| Advanced Features | Multiple SMBus addresses |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 2 |
| Diff. Termination Resistors | 0 |
| Feedback Input | No |
| Function | Zero Delay Buffer |
| Input Freq (MHz) | 1 - 200 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| Longevity | 2040 四月 |
| MOQ | 490 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 200 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.8V |
| Outputs (#) | 2 |
| PLL | Yes |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 100 |
| Price (USD) | $1.78641 |
| Product Category | PCI Express Clocks |
| Prog. Clock | No |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| VOUT Amplitude Control | No |
| VOUT Slew-rate Control | No |
| Width (mm) | 4 |
有关 9DBL0252 的资源
描述
The 9DBL0252 2-output zero-delay/fanout buffer is a 3.3V member of Renesas' full-featured PCIe family. The 9DBL0252 supports PCIe Gen 1 through Gen 6 and both Common and Independent Reference Clock architectures.
For information regarding evaluation boards and material, please contact your local sales representative.