封装信息
| Lead Count (#) | 40 |
| Pkg. Type | VFQFPN |
| Pkg. Code | NDG40 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Pkg. Type | VFQFPN |
| Lead Count (#) | 40 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Price (USD) | 1ku | 2.57863 |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 250 |
| Additive Phase Jitter Typ RMS (ps) | 0.25 |
| Advanced Features | Multiple SMBus addresses |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 1.8 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 6 |
| Diff. Termination Resistors | 16 |
| Divider Value | 1 |
| Feedback Input | No |
| Function | Zero Delay Buffer |
| Input Freq (MHz) | 30 - 175 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| Longevity | 2040 4月 |
| MOQ | 490 |
| NXP Processor Function | SerDes Clock |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 200 |
| Output Impedance | 100 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 8 |
| PLL | Yes |
| Package Area (mm²) | 25.0 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Power Consumption Typ (mW) | 53 |
| Prog. Clock | No |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
描述
The 9DBV0641 6-output 1.8V PCIe fanout clock buffer is a member of Renesas' very-low power PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection to 100Ω transmission lines. The device has six output enable pins for clock management and three selectable SMBus addresses.