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In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.

Watch the Video Series Below

• PCIe Clocking Architectures (Common and Separate)
• PCIe Separate Reference without Spread Clock Architecture
• PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview

Transcript

Hi, this is Ron Wade again with IDT. Today in this little episode we're gonna talk about PCI Express common clocking and its impact on the timing solutions that you would use in the system. So, as the name implies, common clocking says that all of the clocks come from one source. In this case it's a PLL. It may be spreading, it may not, but very seldom do you get all of your clocks from one device, so you'll need some sort of fan out buffers to distribute extra copies of the PCI Express clocks.

And while it's still a common clock, now we have to take into account whether we're using spread spectrum or whether we're using non-spread spectrum. If we are not using SFC, then we can fan out to these buffers here, and this could be a ZDB with a PLL inside, or it could be a fan out buffer, or it could be a part where you select between the two. Without spread spectrum, I can put this buffer in PLL mode or ZDB mode, it doesn't really matter and I don't violate the common clock requirement from the PCI Express sig. Same with this guy, it could be a fan out buffer or a PLL, ZDB, it doesn't really matter.

Things get really interesting though when spread spectrum is in use. When spread spectrum is in use then I have to have...this is my common clock. With spread spectrum in use, these have to be in fan out buffer mode. They cannot be used in PLL mode. And there's a couple of reasons for that, the simplest reason is that if this were a PLL, ZDB and it is tracking the spread, there will always be some tracking error, which means that as the input clock goes like this, the output clock is gonna overshoot it and go down like that. That's just the nature of having a PLL with finite bandwidth. So, you have tracking error here, and the tracking error will cause this to fall out of the PCI Express PPM limitations of +5,300 to -5,300 when you're using a half percent down-spread clock. So with SFC, you have your spread spectrum clock generator but any fan out buffer, any buffering at all has to be a fan out buffer without a PLL. That's a limitation on the architecture.

So the other point I'd like to make is as far as the jitter is concerned, because we're using a common clock here, to assume that the jitter on both sides for the clock is the same and all we have to do is take the difference function...that's a minus sign...the difference between the CPU and the CPU transmitter, say in the I/O storage receiver to calculate our jitter. That'll be more important when we get to the separate clocking in a future video.

In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.

Watch the Video Series Below

• Edit Video page PCIe Clocking Architectures (Common and Separate)
• PCIe Common Clock Architecture and its Impact on Clocking
• PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview

This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.

Watch the Video Series Below

• PCIe Clocking Architectures (Common and Separate)
• PCIe Common Clock Architecture and its Impact on Clocking
• PCIe Separate Reference without Spread Clock Architecture

Transcript

Hi, there. This is Ron Wade with IDT, and we're going to talk about separate reference independence spread today, which is the latest PCI express clocking architecture. So let's jump right in and define it and see what the implications are. So we have the CPU block here and we have our IO storage block here, and in this case they're both being clocked by a spreading clock source, two separate spreading clock sources, and we have the PCI link between them. So the whole idea of doing this is to keep from having to send the clock over this, let's say it's a cable, keep it from sending a clock over the cable like you have to do today.

So one of the implications of this, one is you don't have to send the clock over the cable when you have an SRIS system, but there's some other things to take into account, too. The first is the minimum PPM on this spreading clock is minus 5300 for the PCI, say. The maximum is plus 300 PPM. In this situation, this clock could be at minus 53. This could be at 300, but that means is that this link here has to...the controllers have to, number one, know they're in SRIS mode, and then insert what's called the skip ordered set or dummy data into the link. When you do that, you're going to lose from 1 to 3% of your performance. And the second issue here is there's no mechanism today for the ends of the link to know that they need to be in SRIS mode to insert those skip ordered sets. So there's no mechanism to say, "Hey, SRIS mode, please."

So the second item or the next item is that besides the difference in jitter performance between the transmitter and the receiver and the difference between the jitter of the clock over here and the clock over here, now we have two separate spreads to take into account, and I've drawn the frequency harmonics, the 32 kilohertz of harmonics here. So these have to be taken into account so there's a difference of the spreads also has to be noted. So it's much more stringent to have a clock that meets this requirement than the other architectures already discussed.

So the specifications, they're not final from the PCI-SIG on what a clock has to do to meet these requirements. Based on early indicators, we believe that we have clocks that are SRIS compatible today, and we can talk with you much more about that on one-on-one. So that's a high level overview of SRIS, a couple of system architectures you usually have to look out for, and if you have any questions, you can email me at [email protected]. Thanks.

IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).

Presented by Ron Wade, PCI Express timing expert.

Related Resources

• PCI Express (PCIe) Clocks

Transcript

Hi there. This is Ron Wade with IDT, and today we're gonna give you the lowdown on low power HCSL outputs in a nutshell. But first, we have to understand what standard HCSL outputs are. These are used to clock PCI Express systems for the most part. And we have the standard HCSL which is a...basically, it's a constant current type of output. We have a current source providing 15 milliamps, and we steer the current between the true and the complement outputs. And you can see here, the current is being steered to the complement output, so this 15 milliamps goes out this resistor in series with the output and then it hits the...a pulldown resistor. So you got the current flow going this way, and then this way. And so this 15 milliamps goes through here, which is typically 33 ohms and then goes through this resistor which is 49.9 ohms, and that result is you get your 750 millivolts on the line here. And then when the current is switched, you've got the 750 millivolts on the line, and when you disconnect the current source, the voltage, the charge on the line dissipates through this resistor to ground. And that's how this thing works, you're constantly steering a current back and forth. It's 15 milliamps per output for 100 ohm loads, and that's roughly from 3.3 volts, that is roughly 50 milliwatts per output, which is kind of high.
 
The low-power HCSL outputs are sometimes referred to as push-pull outputs, because on the complement, the true line here, we actually have two transistors, which are actually yanking the signal between ground and this thing called VDDO. In this case, VDDO is a constant voltage source which would be set at approximately 750 millivolts for the high voltage. And then you have one common control line here, which when the complement is shorted to the VDDO rail, the true would be shorted to ground through the transistor and vice versa. That's why it's called push-pull. We're actually pushing and pulling the signal up and down. And because we're pulling the signal down to ground back through this path, there's no shunt resistor to ground on this termination. We only have series resistors. Power consumption-wise, this is a...in a 10-inch trace and a hundred megahertz, it's about five milliamps. So you're already one-third the power of the other guy, and because this is a voltage source or a voltage regulator, you can actually power this from something less than 3.3 volts and save more power. So you save power, you have the ability to cut the termination resistors in half, and actually, you can actually with this technology, bring these series terminations inside for the most density on your board. That's low-power HCSL in a nutshell. Thanks.

An overview of IDT's full-featured PCI Express (PCIe) clock generators addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.

Presented by Ron Wade, System Architect at IDT. For more information about PCIe clock generators visit https://www.renesas.com/products/clocks-timing/application-specific-clocks/pci-express-clocks.

TRANSCRIPT

Hi there, this is Ron Wade with IDT again, and this is the second in our five-part series on the full-featured PCIe clocks. This time we're going to be talking about clock generators. So the full-featured PCIe clock generators, specifically, in this case, the 3.3V parts are the 9FGL02 through 9FGL08. As the names imply, those are 2-output to 8-output devices, and there are also four and six output parts available.
 
So, these are in production now. Everything's on the website for these parts. They are PCI Express gen 1 through 4, common clock, and gen 2-3 SRIS compliant. When you're not using spread spectrum on these parts the 12k to 20M phase jitter on the differential outputs is under 2 picoseconds rms, and that applies to the 3.3-volt parts. We have 100 ohm output devices or 85 ohm output devices in the 3.3-volt range. All the clock generators have a reference output which can be used to save an XO on the board. And the clock generators come in 4x4 to 6x6 mm QFN packages.
 
With the 3.3-volt parts we do have OTP customization at the factory available. You can refer to the data sheets on the web to see what parameters are customizable. And then we also have the complete range of clock generators available in both 1.5V and 1.8V versions. There's some additional features common to these parts and all the parts in the family, you can see in the first part - the family overview in this series.
 
So again, we're just reviewing the key features. The phase jitter is gen 1 through 4, common clock, gen 2-3, SRIS. So you can design these parts in today and use them for a couple of generations before you have to redesign your board. All the parts, the 3.3-volt parts are 200 milliwatts typical for the clock gen, which is very low power. That's 80% power reduction compared to our legacy 9FG108 type parts. So the heat dissipation is reduced, and if you're in a system that requires Energy Star compliance this will definitely help you get there.
 
The integrated terminations in the clock generators save up to 32 resistors which is 55 mm² of board area, which reduces both your BOM and the area requirements of the devices. So the full-featured PCIe clock generators, besides having two, four, six, or eight outputs have one reference clock output, as I mentioned earlier. And this is basically a family comparison of the clock architecture supported - TBD on the 1.8-volt and 1.5-volt parts for gen 4 - and pin compatibility also across the three operating voltages.
 
So IDT has a lot of legacy clock generators in the market, so in this case I took the 55705 along with its PCI Express gen 1 and gen 2 equivalent devices to see why would you want to use a 9FGL04 in place of these four output legacy clock generators. Well, first of all, and the point I'd like to really emphasize, is you are getting much better phase jitter performance. The biggest gap, or the biggest improvement, is probably in the gen 2 Hi band area where you go from 2 and 1.8 picoseconds rms down to 1 picoseconds rms, and these numbers are always spread spectrum on. And then the gen 3 and gen 4 jitter number is 0.32, which means that you've got a lot of margin to the proposed 0.5 picoseconds PCIe gen 4 specification. And these are all for the common clock architecture, by the way.
 
You also get the 12k to 20M jitter with spread off of under 2 picoseconds rms, which is not available on the legacy devices. Your board area goes from over 64 mm², and that then includes the package and the termination resistors, by the way, down to a 25 mm² foot print. And power drops by over 50% from as high as 380 milliwatts down to a 142 milliwatts. And you get the reference outputs which saves you a crystal oscillator. So you've got 25% to 400% less phase jitter, 66% less area, 50% to 90% less power, 16 resistors taken off the BOM. And if you want to save more power, you can use a 1.8-volt or 1.5-volt device for even more power savings.
 
Thank you, that's it for clock generators, part two of our series.

An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.

Presented by Ron Wade, System Architect at IDT.

Related Resources

• PCI Express (PCIe) Clocks
• Clock Buffers, Fanout Buffers, and Clock Drivers

Transcript

Hi there, this is Ron Wade. Welcome back to the last part of our series on full-featured PCIe clocks, part five of five, where we will discuss some of the applications for these parts. So, PCI Express applications are everywhere. The traditional places you might think to find them, such as data centers and servers and storage are still there. But PCI Express is growing into areas such as digital cameras, automotive infotainment systems, and consumer entertainment systems, as well.
 
We have a huge range of parts all the way from the smallest consumer application, to that largest networking and data center application. And the full-featured PCI Express family provides those enterprise levels of performance at the consumer size levels of space, power, and cost.
 
So one of the key applications for the full-featured PCIe family is PCI Express riser cards, where you are basically taking one clock from a connector and providing multiple clocks to additional connectors. Here I've shown the 9DBL02 device in a motherboard application where the riser card has two slots on it. So there would be a 9DBL02 fanout buffer either on the card itself, most likely, taking the clock from the system board and providing two copies, one to each of the connectors.
 
So, these parts again, common across all the full-featured devices. The performance levels against the PCI Express specifications give you reduced video error rates and then the zero delay buffers in this application help you manage PCI Express transport delay, although you can also use either this part in the fanout buffer mode or the pure fanout buffers as well. Again, the parts are offered in a 100ohm output impedance for that environment, and 85ohm output impedance which is often seen in the Intel application space.
 
Another key application for these is with embedded SoCs and here we're using an NXP QorIQ device that would be running in a single oscillator source clock mode, where the only clock into the SoC is a 100 MHz PCI Express clock, in this case coming from a 9FGL0841. These devices often have PCI Express SerDes on them, so I've shown this part driving two SerDes inside the NXP processor. And given that the A41 has eight output pairs, that leaves five additional outputs to drive other devices. I've also shown the pin out over here on the right. It's a 48-pin, 6x6 QFN and the footprint is shown at the bottom illustrating the 6x6 nature of the package.
 
The other growing application, key application, is PCI Express storage or sometimes called NVME. You've got PCI Express drives that are plugged into some sort of mezzanine or riser card. I've shown an IDT retimer in the brown box here, and you've got a system board which has PCI Express data going into the retimer, going up to the drives. Now the system board may be providing you with a clock, and if it is, then you would use a 9DBL device. A five output part is ideal because you've got one clock then going to the PCIe retimer and the other four clocks going to the four drives that are illustrated here. 
 
If you're in an SRIS environment, the system board may not be providing you with a clock, in which case you would use a 9FGL device to generate the clocks. In this case, you would use the six-output part and have an extra one left over for other users, and it would drive the retimer and the four drives. That's it for the series, actually, of full-featured PCI Express parts. Thank you very much for watching and I hope you enjoyed it and learned something. Thanks.

A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.

Presented by Ron Wade, system architect at IDT. For more information about IDT's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.

A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information, visit Renesas's PCIe Timing Solutions page.

A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.