特性
- PCIe Gen 1–7 compliant
- PCIe Gen 7 Common Clock jitter < 41fs RMS
- 276fs RMS typical phase jitter at 156.25MHz (12kHz to 20MHz)
- 2 programmable output pairs plus 1 LVCMOS REF output
- 1 integer, fractional or spread-spectrum output frequency per configuration
- 1MHz to 325MHz output frequency (LVDS or LP-HCSL)
- 1MHz to 200MHz output frequency (LVCMOS)
- 1.8V to 3.3V core VDD
- Individual 1.8V, 2.5V, or 3.3V VDDO for each programmable output pair
- Supports HCSL, LVDS, and LVCMOS I/O standards
- Supports AC-coupled LVPECL and CML logic – See AN-891
- 3mm × 3mm 16-LGA packages with 50MHz integrated crystal option
- Supported by Timing Commander™ software
描述
The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides two copies of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 2 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 |
| Outputs (#) | 2 |
| Output Type | LP-HCSL |
| Output Freq Range (MHz) | 100 - 100 |
| Input Freq (MHz) | 25 - 25, 50 - 50 |
| Inputs (#) | 1 |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8, 3.3 |
| Output Voltage (V) | 1.8, 3.3 |
| Product Category | PCI Express Clocks |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| LGA | 3.0 x 3.0 x 1.1 | 16 | 0.5 |