特性
- PCIe Gen6 phase jitter < 40fs rms
- 3 x 25MHz dedicated output pairs
- 7 x 100MHz dedicated output pairs with individual OE# pins
- 9 MXCLK output pairs multiplexable between 100MHz and 25MHz
- 3.3V operation
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 80 resistors, saving 130mm2 of area
- 9 selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- OE# pin control of 100M[6:0] supports PCIe slot CLKREQ#
- Dedicated Platform Time input and output clocks (PFT_IN and PFT_OUT)
- 8 × 8 mm dual-row 100-VFQFPN
- -40°C to +85°C operating temperature range
描述
The 9SQ440 is an Intel CK440 main clock synthesizer for Intel cloud and HPC platforms, and newer Intel-based server platforms. 9SQ440 is a single-chip, PCIe Gen6 compliant, and is designed to work as a complete clock solution or in combination with DB2000Q-compliant clock buffers to provide point-to-point clocks to multiple receiving agents.
产品参数
属性 | 值 |
---|---|
Function | Generator |
Architecture | Common, SRIS, SRNS |
App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 |
Diff. Outputs | 20 |
Diff. Output Signaling | LP-HCSL |
Output Impedance | 85 |
Power Consumption Typ (mW) | 875 |
Supply Voltage (V) | 3.3 - 3.3 |
Advanced Features | 25MHz output(s), 100MHz output(s), Spread Spectrum, PFT |
封装选项
Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
---|---|---|---|
VFQFPN | 8.0 x 8.0 x 0.55 | 100 | 0.5 |
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A brief comparison of PCI Express (PCIe) Gen3-7 common clock jitter filters vs. a typical 12k to 20MHz plot. Presented by Ron Wade, System Architect at Renesas.
For more information, visit the PCI Express Clocks page.